1 ? fn3141.4 HI-1818A low resistance, singl e 8-channel, cmos analog multiplexer the hl-1818a is a monolithic, high performance cmos analog multiplexer offering built-in channel selection decoding plus an inhibit (enable) input for disabling all channels. dielectric isolation (dl) processing is used for enhanced reliability and performance. substrate leakage and parasitic capacitance are much lower, resulting in extremely low static errors and high throughput rates. low output leakage (typically 0.1na) and low channel on resistance (250 ? ) assure optimum performance in low level or current mode applications. the HI-1818A is a single-ended, 8-channel multiplexer, and is ideally suited for medical instru mentation, telemetry systems, and microprocessor based data acquisition systems. features ? signal range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15v ?on? resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ? input leakage (max) . . . . . . . . . . . . . . . . . . . . . . . . .50na access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns power consumption . . . . . . . . . . . . . . . . . . . . . . . . .5mw dtl/ttl compatible address operation . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c applications data acquisition systems precision instrumentation demultiplexing selector switch ordering information part number temp. range ( o c) package pkg. dwg. # hi1-1818a-2 -55 to 125 16 ld cerdip f16.3 pinout HI-1818A (cerdip) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 address a 1 +5v supply enable address a 2 in 8 in 7 in 5 in 6 address a 0 +v supply in 1 out in 2 in 3 in 4 -v supply data sheet november 19, 2004 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002, 2004. all rights reserved
2 fn3141.4 november 19, 2004 truth table functional block diagram HI-1818A HI-1818A truth table address ?on? channel a 2 a 1 a 0 en llll 1 llhl 2 lhll 3 lhhl 4 hlll 5 hlhl 6 hhl l 7 hhhl 8 xxxh none HI-1818A truth table address ?on? channel a 2 a 1 a 0 en n a 0 a 1 a 2 enable digital address enable buffer decoders p multiplex switches n p in 1 out in 8 address input buffers schematic diagrams all n-channel bodies to v- all p-channel bodies to v+ unless otherwise specified address input buffer n9 p9 n10 p10 n8 p8 n7 p7 n6 p6 n5 n4 n3 v- n1 p1 p2 n2 p5 p4 v cc v+ v- address input d1 d2 200 ? p3 a a HI-1818A
3 fn3141.4 november 19, 2004 all n-channel bodies to v- all p-channel bodies to v+ address decoder all n-channel bodies to v- all p-channel bodies to v+ unless otherwise specified multiplexer switch schematic diagrams v+ v- a0 or a0 n14 n13 a1 or a1 n12 n11 a2 or a2 en p14 p13 p12 p11 n15 p15 n16 p16 to p-channel switch to n-channel switch in switch cell v+ n18 n17 n19 p17 p18 from decode from decode v+ out in HI-1818A
4 fn3141.4 november 19, 2004 absolute maximum ratings thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40v logic supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30v analog signal (v in , v out ). . . . . . . . . . . . . . . . . (v-) -2v to (v+) +2v digital input voltage (v en , v a ) . . . . . . . . . . . . . . . . . . . . (v-) to (v+) operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 80 20 maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective therma l conductivity test board in fr ee air. see tech brief 379 for details. electrical specifications supplies = +15v, -15v, +5v; v al = 0.4v, v ah = 4.0v, unless otherwise specified parameter test conditions temp ( o c) min typ max units dynamic characteristics access time, t a note 4 25 - 350 500 ns full - - 1000 ns break-before-make delay, t open 25 - 25 - ns enable delay (on), t on(en) 25 - 300 500 ns full - - 1000 ns enable delay (off), t off(en) 25 - 300 500 ns full - - 1000 ns settling time to 0.1% 25 - 1.08 - s to 0.025% 25 - 2.8 - s channel input capacitance, c s(off) 25 - 4 - pf channel output capacitance, c d(off) 25 - 20 - pf input to output capacitance, c ds(off) 25 - 0.6 - pf digital input capacitance, c a 25 - 5 - pf digital input characteristics input low threshold, v al full - - 0.4 v input high threshold, v ah note 3 full 4.0 - - v input leakage current, i a full - - 1 a analog channel characteristics analog signal range, v ln full -15 - +15 v on resistance, r on note 2 25 - 250 400 ? full - - 500 ? off input leakage current, i s(off) full - - 50 na on channel leakage current, l d(on) full - - 250 na off output leakage current, i d(off) full - - 250 na HI-1818A
5 fn3141.4 november 19, 2004 power supply characteristics power dissipation, p d full - - 27.5 mw current, i+ full - - 0.5 ma current, i- full - - 1 ma current, i l full - - 1 ma notes: 2. v out = 10v, i out = 1ma. 3. to drive from dtl/ttl circuits, 1k ? pull-up resistors to 5. 0v supply are recommended. 4. time measured to 90% of final output level; v out = -5.0v to 5.0v, digital inputs = 0v to 4.0v. electrical specifications supplies = +15v, -15v, +5v; v al = 0.4v, v ah = 4.0v, unless otherwise specified (continued) parameter test conditions temp ( o c) min typ max units test circuits and waveforms figure 1a. measurement points figure 1b. test circuit figure 1c. waveforms figure 1. enable delays figure 2a. measurement points figure 2b. test circuit figure 2c. waveforms figure 2. break-before-make delay v ah = 4.0v v al = 0v output 10% t off (en) 90% t on (en) 50% enable drive (v a ) +15v v a +5v -15v +5v v+ v- v l in 1 in 2-8 out HI-1818A 200 12.5 ? 50 ? a 0 en a 1 a 2 pf enable drive 2v/div. output 2v/div. 100ns/div. enabled (s 1 on) disabled 50% 50% 0v 4.0v address drive (v a ) t open output +15v v a +5v -15v +5v v+ v- v l in 1 in 2 in 3-8 out HI-1818A 50 ? a 0 en a 1 a 2 200 12.5 ? pf v a input 2v/div. output 1v/div. 100ns/div. s 2 on s 1 on HI-1818A
6 fn3141.4 november 19, 2004 figure 3. on resistance vs analog input voltage figure 4. on channel current vs voltage figure 5. leakage currents vs temperature figure 6. access time 350 300 250 200 150 100 -10-8-6-4-20246810 analog input (v) on resistance ( ? ) 125 o c 25 o c -55 o c out in v in v 2 1ma r on = v 2 1ma 60 20 0 -20 -40 -60 -10-8-6-4-20246810 voltage across switch (v) switch current (ma) 40 out v a 25 o c -55 o c 125 o c -55 o c 125 o c 25 o c out en out 10v en 4v + 10v a i d(off) 10v a i s(off) 4v + 10v out 10v en 0.4v + 10v a i d(on) a 0 a 1 off leakage on leakage note: two measurements per channel: 10v and 10v two measurements per device for i d(off) : 10v and 10v 100na 10na 1na 100pa 10pa 25 50 75 100 125 temperature ( o c) HI-1818A i d(on) - i d(off) i s(off) HI-1818A 100ns/div. a 0 input 2v/div. 50 ? 50pf en a 0 access time test circuit a 1 a 2 HI-1818A 0v to 4v in 3-8 in 2 in 1 -5v +5v 10 k ? 4v 50% +5v output 5v/div. -5v 10% t a out HI-1818A
7 fn3141.4 november 19, 2004 die characteristics metallization: ty p e : c u a l thickness: 16k ? 2k ? passivation: type: nitride/silox thickness: silox: 12k ? 2k ? , nitride: 3.5k ? 1k ? worst case current density: 1.43 x 10 5 a/cm 2 at 25ma metallization mask layout HI-1818A v l a 1 a 0 -v supply +v supply in 1 output in 2 in 3 in 4 in 5 in 6 in 7 in 8 a 2 en HI-1818A
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3141.4 november 19, 2004 HI-1818A ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f16.3 mil-std-1835 gdip1-t16 (d-2, configuration a) 16 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n16 168 rev. 0 4/94
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